An analogous method, for a multiprocessor architecture, is known from the technical bulletin of Digital Equipment Corporation dated Oct. 2, 1991 and entitled "A methodology for implementing highly concurrent data objects". Its main purpose is to manage concurrent accesses to a memory by a plurality of processors in a fault-tolerant context. The invention relates more particularly to a method of managing concurrent accesses to a memory by a plurality of activities (referred to as "threads") in a single-processor context.
This type of multi-thread processing serves to manage very fast interchanges of data between asynchronous tasks that transmit and receive such data. Each data item transmitted by a task is picked up by a thread that records it in a zone of the memory identified by the value of a write index. When a task requires a data item, a thread proceeds to read a data item from the memory zone identified by a read index. At each read or write stage in the memory, the read index or the write index is updated for the next read or write operation.
The main problem in using a memory that is shared between a plurality of concurrent threads is ensuring the integrity of the data interchanged between the threads. This problem can be presented as follows.
A thread A begins to write data into a memory zone identified by the write index.
Shortly thereafter, a thread B begins to write data into the same memory zone, even though the write index has not been updated in the meanwhile.
This gives rise to mixed-up data belonging to both threads A and B, since neither of those two threads has been able to use the memory for its own account only.
If ever a thread C reads from that memory zone, then it will recover data that is incoherent relative to the write operations of threads A and B.
A solution known from the above-mentioned document is to ensure that each user of the memory reads or writes a data item into a memory zone by causing an atomic sequence of instructions to be performed, i.e. a sequence of instructions that cannot be interrupted by any other user.
In that document, the sequence of instructions makes use of an operation for setting a latch, and if successful, it enables the user who has set the latch to have exclusive access to the memory until that user releases the latch. One possible implementation of setting and releasing a latch by applying instructions of the "store-conditional" type and of the "load-linked" type is described in the above-mentioned document. While a user has exclusive access to the memory, other users in waiting seek to gain access to the memory.
The drawbacks of such a method are as follows.
If the user who has set the latch goes into a loop, then all the other users waiting for access to the memory are blocked. Further, if the users who share the memory are operating in a real time context, then the execution time of a sequence of instructions used by one of the users for accessing the memory can exceed the response time imposed on other users which share access to that memory. As result, that known method is unsuitable for real time processing.
In that known method, the atomic sequence of instructions performed by a processor on behalf of a user includes operations of reading or writing data in a zone of the memory. That atomic instruction sequence is referred to as a "critical section".